The present invention relates generally to PCI-X systems and, more particularly, to management of read transactions in PCI-X controlled systems. Even more particularly, the present invention provides a mechanism to process data transactions using a buffer page roll.
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
A conventional computer system typically includes one or more central processing units (CPUs) and one or more memory subsystems. Computer systems also include peripheral devices for inputting and outputting data. Some common peripheral devices include, for example, monitors, keyboards, printers, modems, hard disk drives, floppy disk drives, and network controllers.
One of the important factors in the performance of a computer system is the speed at which the CPU operates. Generally, the faster the CPU operates, the faster the computer system can complete a designated task. One method of increasing the speed of a computer is using multiple CPUs, commonly known as multiprocessing. However, the addition of a faster CPU or additional CPUs can result in different increases in performance among different computer systems. Although it is the CPU that executes the algorithms required for performing a designated task, in many cases it is the peripherals that are responsible for providing data to the CPU and storing or outputting the processed data from the CPU. When a CPU attempts to read or write to a peripheral, the CPU often xe2x80x9csets asidexe2x80x9d the algorithm that is currently executing and diverts to executing the read/write transaction (also referred to as an input/output transaction or an I/O transaction) for the peripheral. As can be appreciated by those skilled in the art, the length of time that the CPU is diverted is typically dependent on the efficiency of the I/O transaction.
Although a faster CPU may accelerate the execution of an algorithm, a slow or inefficient I/O transaction process associated therewith can create a bottleneck in the overall performance of the computer system. As the CPU becomes faster, the amount of time executing algorithms becomes less of a limiting factor compared to the time expended in performing an I/O transaction. Accordingly, the improvement in the performance of the computer system that could theoretically result from the use of a faster CPU or the addition of additional CPUs may become substantially curtailed by the bottleneck created by the I/O transactions. Moreover, it can be readily appreciated that any performance degradation due to such I/O bottlenecks in a single computer system may have a stifling affect on the overall performance of a computer network in which the computer system is disposed.
As CPUs have increased in speed, the logic controlling I/O transactions has evolved to accommodate these transactions. Thus, most I/O transactions within a computer system are now largely controlled by application specific integrated circuits (ASIC). These ASICs contain specific logic to perform defined functions. For example, Peripheral Component Interconnect (PCI) logic is instilled within buses and bridges, which govern I/O transactions between peripheral devices and the CPU. Today, PCI logic has evolved into the Peripheral Component Interconnect Extended (PCI-X) to form the architectural backbone of the computer system. PCI-X logic has features that improve upon the efficiency of communication between peripheral devices and the CPU. For instance, PCI-X technology increases bus capacity to more than eight times the conventional PCI bus bandwidth. For example, a 133 MB/s system with a 32 bit PCI bus running at 33 MHz is increased to a 1066 MB/s system with the 64 bit PCI bus running at 133 MHz.
An important feature of the new PCI-X logic is that it can provide backward compatibility with PCI enabled devices at both the adapter and system levels. Backward compatibility allows PCI controlled devices to operate with PCI-X logic. Although the devices will operate at the slower PCI speed and according to PCI specifications, the devices may be compatible to the new logic governing PCI-X transactions. Furthermore, PCI-X devices will run according to PCI-X specifications, while PCI devices will operate according to PCI specifications without having an adverse affect on the PCI-X devices.
PCI-X logic allows a requesting device to make only one data request and relinquish the bus, rather than holding the bus to poll for a response. PCI-X logic also enables the requesting device to specify in advance the specific number of bytes requested, thus eliminating the inefficiency of prefetches. Additionally, PCI-X bus logic incorporates an attribute phase, split transaction support, optimized wait states, and standard block size movement.
PCI-X logic provides an attribute phase that uses a 36-bit attribute field which describes bus transactions in more detail than the conventional PCI bus logic. This field includes information about the size of the transaction, the ordering of transactions, and the identity of the transaction initiator. Furthermore, the attribute field in the PCI-X standard incorporates the transaction byte count, which allows the bridge to determine exactly how much data to fetch from the memory. The attribute phase feature of PCI-X logic also incorporates relaxed ordering, sequence number, transaction byte count, and non-cache-coherent transactions.
As PCI-X logic is incorporated into the next generation of buses, it becomes important to handle transaction requests efficiently. Generally, peripheral devices initiating read block transactions target the PCI-X bridge. As a transaction is initiated, a buffer is allocated within the bridge. The bridge stores the information about the transaction, such as its starting address, length and so on. In the PCI-X specification, split transactions require the bridge logic to generate a reply transaction with the requested data. Thus, the PCI-X bridge stores the transaction in a queue and replies to the transaction according to priority. Normally, a buffer holding a read block transaction is restricted to containing data within a certain memory boundary, and these queues have limitations on the address boundaries a transaction can cross. Particularly, if the data string crosses a memory boundary then the transaction will not be completed properly. Instead, it will be delivered to the requester incomplete. Although PCI-X specification allows read transactions to cross any address boundary, only the data that does not cross the memory boundary will be delivered to the requester.
The present invention may address one or more of the problems discussed above.
Certain aspects commensurate in scope with the originally claimed invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, there is provided a computer system that provides ordering of a sequence of events to complete a transaction. When a data transaction is initiated to a computer system, a series of events occurs to efficiently reply to the transaction. At the time a transaction is made, the system logic inquires whether the transaction is governed by PCI-X specifications. Specifically, the PCI-X transaction inquiry generally occurs at the bridge or bus level. As a transaction is initiated, a buffer is allocated for the storage of data. If the transaction is governed by PCI-X specifications rather than the conventional PCI specifications, the system determines whether the transaction is a read block transaction. Next, the data requested is separated into a part before a memory boundary and a second part after the memory boundary. The data within the first part of the memory boundary is read and returned to the requester. Once the data within the first part of the memory boundary is returned to the requester, the system initiates a page roll., whereby the data which crosses the memory boundary is read and returned to the requester.
The invention monitors the data flow, delivers the data within the memory boundary to the initiator, and retains the data, which crosses the memory boundary. As the data is returned to the requester, the invention replaces the starting address of the separated data string with the memory boundary address. The invention also replaces the number of bytes requested, with the number of bytes beyond the memory boundary. The system reads the remaining data requested and delivers it to the requester. This completes the PCI-X transaction.
In accordance with another aspect of the present invention, there is provided a computer system that provides ordering of a sequence of events for a specific transaction using a plurality of buffers. Specifically, the system allocates a plurality of buffers for a single PCI-X transaction that crosses a memory boundary. As a transaction is initiated, two buffers are allocated to a single read block transaction. Moreover, in this particular embodiment, a page roll is not required, but instead the data is read using the two buffers. The data requested is stored within a plurality of buffers, and returned to the requester, according to the PCI-X ordering rules.